Electrically Erasable Programmable Read Only Memory Devices (EEPROMs) and methods for making such devices are well known in the art. One such device, called a flash EEPROM, is disclosed in U.S. Pat. Nos. 4,698,787 and 4,868,619 to Mukherjee et al, and assigned to assignee of the subject application, which are hereby incorporated by reference. A flash EEPROM memory is formed of a high density (e.g. on the order of 1 megabit) array of cells. Each cell is a single-transistor device comprising a body of single crystalline semiconductive material having a source, a drain and a first layer of insulating material positioned on the body. A floating gate is positioned between the first layer of insulating material and a second layer of insulating material, and a gate is positioned over the second layer of insulating material.
The source is formed of a deep region of a first material, such as phosphorous, and a shallower region of a second material, such as arsenic and phosphorus. A portion of the deep region underlies the first layer of insulating material and the first material is selected to optimize the junction overlap with the gate, in order to reduce band to band tunneling during the erase operation. The drain is formed of a shallow region of the second material.
The second layer of insulating material has a high dielectric constant so as to optimize its capacitance. This maximizes the voltage across the floating gate with respect to the substrate and thereby maximizes the ability of the device to store or remove charge on its floating gate.
Programming of a conventional flash EEPROM cell requires applying voltages of approximately 10 V to 12 V and 4 V to 6 V to the control gate and drain, respectively, and holding the source and the substrate at a ground potential. This voltage condition causes hot electrons to be generated from a portion of the substrate (the channel region) lying between the source and drain and to be accelerated onto the floating gate. To erase a flash EEPROM cell, a voltage of between 10 V to 13 V is applied to the source while the drain is floated and the control gate and substrate are held at ground potential. In this way, electrons pass from the floating gate into the source region by Fowler-Nordheim tunneling.
During a read operation, the logical condition of a cell is determined by applying a 1 V to 2 V potential to the drain, a 3 V to 6 V potential to the control gate, and a ground potential to the source. Because a programmed cell has an elevated voltage threshold (Vt) due to the presence of electrons on the floating gate, the channel region of the programmed cell will not conduct during the read operation. On the other hand, an erased cell will have a threshold voltage of approximately 1 V and so its channel region will conduct during a read operation.
Several disadvantages have been associated with conventional flash EEPROM technology. One such disadvantage lies in the use of hot electron injection programming. This programming consumes a great deal of current, making it a technology that precludes the use of internal, on-chip charge pumps when a low voltage (less than 5 volts) supply is used.
Other disadvantages of the current flash EEPROM technology arise from factors which affect cell endurance. For example, when programming a cell, the drains of all cells sharing a column with the cell to be programmed receive the relatively high drain potential required for programming. This is due to the fact that all cells in a column typically share a common bit line. A disturb condition arises in these unselected cells due to the potential difference between the drains (4 V to 6 V) and the substrate (which is held at ground potential). The relatively high voltage drop between the drain and substrate during programming can lead to the formation of hot holes at the drain junctions. These hot holes can migrate onto the gate dielectric and become trapped them permanently, leading to premature failure of the cell.
Hot holes trapped in the gate dielectric will interfere with the read operation of the device and will cause a decrease in the energy barrier between the substrate and the floating gate which is normally provided by the gate dielectric. The decrease in this energy barrier will in turn cause electrons to migrate onto the floating gate of unselected cells. Generation of hot holes may escalate to the extent that the ,energy level of the hot electrons exceeds that of the electrons, causing band-to-band tunneling which in turn releases additional hot-electron/hot-hole pairs and thus causes further hot hole trapping in the gate dielectric.
Breakdown at the source to substrate junction, which will likewise lead to hot hole generation and trapping, is similarly apt to occur during erasing of conventional flash EEPROM devices because of the high voltage differential between the source (approx. 10 V to 13 V) and the grounded substrate. While this breakdown may be substantially reduced by forming a double diffused source region, adding an additional diffusion layer will not eliminate such effects entirely.
Another disadvantage of present flash EEPROM technology is that over-erased cells cannot be detected bit by bit. An over-erase condition occurs when too many electrons are removed from the floating gate of a cell during erasing, causing the cell to become erased below a Vt of 0 V or to a Vt which causes the cell to conduct even when its word line is deselected. The low threshold voltage of an over-erased cell causes the cell to program and read incorrectly, and over-erased cells normally induce drain leakage current which then masks the logical state of the other cells sharing the same bit line. The presence of an over-erased cell thus cannot be detected bit by bit because when one over-erased cell is present in a column, that cell even when deselected will cause current to flow through the bit line coupled to that column and to thereby obscure the identity of the over-erased cells. Because over-erased cells are difficult to detect, memories found to contain such cells often are discarded, or blocks containing over-erased cells are isolated and replaced with redundant memories. These measures are commonly both costly and inefficient.
Various attempts have been made to develop flash EEPROM devices which minimize the hot hole trapping effects described above. One such device is disclosed in U.S. Pat. No. 5,077,691 to Haddad et al ("Haddad patent"). There a flash EEPROM is disclosed which is erased using Fowler-Nordheim tunneling from the floating gate to the source when a voltage of approximately -17 V to -12 V is applied to the control gate and a voltage of approximately 0.5 V to 5.0 V is applied to the source. Although devices such as that disclosed in the Haddad patent reduce the probability of hot hole trapping effects during erasure, these devices use an elevated drain potential to accomplish programming and thus do not address the drain disturb problem, described above, which occurs in unselected cells. Moreover, programming of these devices is accomplished by hot electron injection programming which as discussed earlier consumes a great deal of current.
Another disadvantage of conventional flash EEPROM devices and devices such as the one disclosed in the Haddad patent is that programming of these devices is accomplished in three steps. First, all cells are programmed to a high Vt by applying the programming conditions for approximately 10 msec. Because hot electron injection is used, this first step uses a high current and thus can only be carried out byte-by-byte. Next, all cells are simultaneously erased using the flash erase function by applying the erase conditions for approximately 10 msec. Finally, data is placed on the chip by programming the cells byte-by-byte, again using a programming pulse of approximately 10 msec in duration. Programming of these chips is therefore time consuming, particularly due to the fact that they require two programming steps both of which are accomplished byte-by-byte.
Yet another disadvantage with present flash EEPROM devices lies in the fact that the use of high positive potentials at the control gates of the memory cells requires the transistors in the surrounding circuitry to be fabricated with sufficiently high breakdown thresholds so as to prevent breakdown during application of the high gate potentials. Thus, in cells in which programming is accomplished by the application of a 21.0 V potential to the control gate, for example, the peripheral devices will have to be constructed to withstand at least 21.0 V of reverse bias potential.
A device is disclosed in Japanese Patent Early Publication No. 57-114282, which uses Fowler-Norheim tunneling between the substrate and the floating gate to program and erase the device. Further, erasing is performed using high voltages on the drain of the device, so that particular care must be taken to avoid breakdown and other problems involving the drain-substrate junction.